1. Field of the Invention
The disclosure relates generally to verification for designs, and, more particularly, to simulation methods and systems for what-if analysis.
2. Description of the Related Art
Due to increasing design complexity, verification has become a major bottleneck in the chip design industry. Various verification methodologies have been adopted to verify whether design behaviors are correct. Among all those approaches, dynamic verification, such as simulation is still one of the major forces used to drive the verification progress.
Generally, simulations must be repeatedly performed due to what-if changes. It is understood that the what-if change may be a design change, a signal value change, or a combination of a design change and a signal value change. Conventionally, when a what-if change is given, the what-if change is applied, and the whole design is re-simulated using a simulator. It is noted that since the whole design is simulated and the simulation for each what-if change may take several hours or several days, it is difficult to conduct many what-if changes, and the turnaround time thereof is troublesome. Further, since the entire design and the what-if change are needed to be re-compiled, the time for compilation is also a concern.